Beamforming for Antenna Arrays BEE2 vs DSP Processors

We present an architecture for highly scalable and reusable time domain beam formers using general-purpose FPGA boards. We also present a comparable architecture for the same using DSP processors. The FPGA design is based on the BEE2[2] platform. System generality and reusability is the focus of our design, which assumes very little about the target antenna array and avoids any sort of tight coupling between subsystems. Our FPGA prototype, which we call BEEmformer is being deployed at the Allen Telescope Array (ATA)[8] in July 2007. At the core of our system is a single all-purpose design, which becomes a recurring motif replicated on all FPGAs across the system. On a single BEE2 board we provide a phasing engine for signals having up to 200MHz bandwidth from 32 antennas while forming 3 simultaneous beams. Multiple boards are connected together to further scale the system arbitrarily in bandwidth, polarization channels, number of simultaneous beams and up to a maximum of 256 antennas, which too is only a soft limit. The connection topology can be modified for any desired configuration on the fly with software control. All communication between subsystems is asynchronous and uses hot-swappable high-speed serial links using industry standard protocols[7]. The globally asynchronous packet processing approach also obviates the need for frequency locked clock distribution. In addition to the above, we have conceptually worked out an architecture for the same instrument using the TMS320C6455, a state of the art DSP processor[1]. DSP processors provide an attractive alternative to FPGAs due to the ease of programming and simulation. We evaluated the performance and data bandwidth of the chip to draw comparisons between the DSP vs. FPGA approaches.